Merge branch 'next/soc-exynos5250-arch' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / arm / boot / dts / tegra30.dtsi
1 /include/ "skeleton.dtsi"
2
3 / {
4         compatible = "nvidia,tegra30";
5         interrupt-parent = <&intc>;
6
7         intc: interrupt-controller@50041000 {
8                 compatible = "arm,cortex-a9-gic";
9                 interrupt-controller;
10                 #interrupt-cells = <3>;
11                 reg = < 0x50041000 0x1000 >,
12                       < 0x50040100 0x0100 >;
13         };
14
15         i2c@7000c000 {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
19                 reg = <0x7000C000 0x100>;
20                 interrupts = < 0 38 0x04 >;
21         };
22
23         i2c@7000c400 {
24                 #address-cells = <1>;
25                 #size-cells = <0>;
26                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
27                 reg = <0x7000C400 0x100>;
28                 interrupts = < 0 84 0x04 >;
29         };
30
31         i2c@7000c500 {
32                 #address-cells = <1>;
33                 #size-cells = <0>;
34                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
35                 reg = <0x7000C500 0x100>;
36                 interrupts = < 0 92 0x04 >;
37         };
38
39         i2c@7000c700 {
40                 #address-cells = <1>;
41                 #size-cells = <0>;
42                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
43                 reg = <0x7000c700 0x100>;
44                 interrupts = < 0 120 0x04 >;
45         };
46
47         i2c@7000d000 {
48                 #address-cells = <1>;
49                 #size-cells = <0>;
50                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
51                 reg = <0x7000D000 0x100>;
52                 interrupts = < 0 53 0x04 >;
53         };
54
55         gpio: gpio@6000d000 {
56                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
57                 reg = < 0x6000d000 0x1000 >;
58                 interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
59                 #gpio-cells = <2>;
60                 gpio-controller;
61         };
62
63         serial@70006000 {
64                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
65                 reg = <0x70006000 0x40>;
66                 reg-shift = <2>;
67                 interrupts = < 0 36 0x04 >;
68         };
69
70         serial@70006040 {
71                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
72                 reg = <0x70006040 0x40>;
73                 reg-shift = <2>;
74                 interrupts = < 0 37 0x04 >;
75         };
76
77         serial@70006200 {
78                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
79                 reg = <0x70006200 0x100>;
80                 reg-shift = <2>;
81                 interrupts = < 0 46 0x04 >;
82         };
83
84         serial@70006300 {
85                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
86                 reg = <0x70006300 0x100>;
87                 reg-shift = <2>;
88                 interrupts = < 0 90 0x04 >;
89         };
90
91         serial@70006400 {
92                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
93                 reg = <0x70006400 0x100>;
94                 reg-shift = <2>;
95                 interrupts = < 0 91 0x04 >;
96         };
97
98         sdhci@78000000 {
99                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
100                 reg = <0x78000000 0x200>;
101                 interrupts = < 0 14 0x04 >;
102         };
103
104         sdhci@78000200 {
105                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
106                 reg = <0x78000200 0x200>;
107                 interrupts = < 0 15 0x04 >;
108         };
109
110         sdhci@78000400 {
111                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
112                 reg = <0x78000400 0x200>;
113                 interrupts = < 0 19 0x04 >;
114         };
115
116         sdhci@78000600 {
117                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
118                 reg = <0x78000600 0x200>;
119                 interrupts = < 0 31 0x04 >;
120         };
121
122         pinmux: pinmux@70000000 {
123                 compatible = "nvidia,tegra30-pinmux";
124                 reg = < 0x70000868 0xd0     /* Pad control registers */
125                         0x70003000 0x3e0 >; /* Mux registers */
126         };
127 };