Merge branch 'samsung/exynos5' into next/soc2
[linux-2.6.git] / arch / arm / boot / dts / tegra30.dtsi
1 /include/ "skeleton.dtsi"
2
3 / {
4         compatible = "nvidia,tegra30";
5         interrupt-parent = <&intc>;
6
7         pmc@7000f400 {
8                 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9                 reg = <0x7000e400 0x400>;
10         };
11
12         intc: interrupt-controller@50041000 {
13                 compatible = "arm,cortex-a9-gic";
14                 interrupt-controller;
15                 #interrupt-cells = <3>;
16                 reg = < 0x50041000 0x1000 >,
17                       < 0x50040100 0x0100 >;
18         };
19
20         apbdma: dma@6000a000 {
21                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
22                 reg = <0x6000a000 0x1400>;
23                 interrupts = < 0 104 0x04
24                                0 105 0x04
25                                0 106 0x04
26                                0 107 0x04
27                                0 108 0x04
28                                0 109 0x04
29                                0 110 0x04
30                                0 111 0x04
31                                0 112 0x04
32                                0 113 0x04
33                                0 114 0x04
34                                0 115 0x04
35                                0 116 0x04
36                                0 117 0x04
37                                0 118 0x04
38                                0 119 0x04
39                                0 128 0x04
40                                0 129 0x04
41                                0 130 0x04
42                                0 131 0x04
43                                0 132 0x04
44                                0 133 0x04
45                                0 134 0x04
46                                0 135 0x04
47                                0 136 0x04
48                                0 137 0x04
49                                0 138 0x04
50                                0 139 0x04
51                                0 140 0x04
52                                0 141 0x04
53                                0 142 0x04
54                                0 143 0x04 >;
55         };
56
57         i2c@7000c000 {
58                 #address-cells = <1>;
59                 #size-cells = <0>;
60                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
61                 reg = <0x7000C000 0x100>;
62                 interrupts = < 0 38 0x04 >;
63         };
64
65         i2c@7000c400 {
66                 #address-cells = <1>;
67                 #size-cells = <0>;
68                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69                 reg = <0x7000C400 0x100>;
70                 interrupts = < 0 84 0x04 >;
71         };
72
73         i2c@7000c500 {
74                 #address-cells = <1>;
75                 #size-cells = <0>;
76                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77                 reg = <0x7000C500 0x100>;
78                 interrupts = < 0 92 0x04 >;
79         };
80
81         i2c@7000c700 {
82                 #address-cells = <1>;
83                 #size-cells = <0>;
84                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85                 reg = <0x7000c700 0x100>;
86                 interrupts = < 0 120 0x04 >;
87         };
88
89         i2c@7000d000 {
90                 #address-cells = <1>;
91                 #size-cells = <0>;
92                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93                 reg = <0x7000D000 0x100>;
94                 interrupts = < 0 53 0x04 >;
95         };
96
97         gpio: gpio@6000d000 {
98                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
99                 reg = < 0x6000d000 0x1000 >;
100                 interrupts = < 0 32 0x04
101                                0 33 0x04
102                                0 34 0x04
103                                0 35 0x04
104                                0 55 0x04
105                                0 87 0x04
106                                0 89 0x04
107                                0 125 0x04 >;
108                 #gpio-cells = <2>;
109                 gpio-controller;
110                 #interrupt-cells = <2>;
111                 interrupt-controller;
112         };
113
114         serial@70006000 {
115                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
116                 reg = <0x70006000 0x40>;
117                 reg-shift = <2>;
118                 interrupts = < 0 36 0x04 >;
119         };
120
121         serial@70006040 {
122                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
123                 reg = <0x70006040 0x40>;
124                 reg-shift = <2>;
125                 interrupts = < 0 37 0x04 >;
126         };
127
128         serial@70006200 {
129                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
130                 reg = <0x70006200 0x100>;
131                 reg-shift = <2>;
132                 interrupts = < 0 46 0x04 >;
133         };
134
135         serial@70006300 {
136                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
137                 reg = <0x70006300 0x100>;
138                 reg-shift = <2>;
139                 interrupts = < 0 90 0x04 >;
140         };
141
142         serial@70006400 {
143                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
144                 reg = <0x70006400 0x100>;
145                 reg-shift = <2>;
146                 interrupts = < 0 91 0x04 >;
147         };
148
149         sdhci@78000000 {
150                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
151                 reg = <0x78000000 0x200>;
152                 interrupts = < 0 14 0x04 >;
153         };
154
155         sdhci@78000200 {
156                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
157                 reg = <0x78000200 0x200>;
158                 interrupts = < 0 15 0x04 >;
159         };
160
161         sdhci@78000400 {
162                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
163                 reg = <0x78000400 0x200>;
164                 interrupts = < 0 19 0x04 >;
165         };
166
167         sdhci@78000600 {
168                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
169                 reg = <0x78000600 0x200>;
170                 interrupts = < 0 31 0x04 >;
171         };
172
173         pinmux: pinmux@70000000 {
174                 compatible = "nvidia,tegra30-pinmux";
175                 reg = < 0x70000868 0xd0     /* Pad control registers */
176                         0x70003000 0x3e0 >; /* Mux registers */
177         };
178 };