First version
[3rdparty/ote_partner/tlk.git] / platform / tegra / monitor / memory.c
1 /*
2  * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining
5  * a copy of this software and associated documentation files
6  * (the "Software"), to deal in the Software without restriction,
7  * including without limitation the rights to use, copy, modify, merge,
8  * publish, distribute, sublicense, and/or sell copies of the Software,
9  * and to permit persons to whom the Software is furnished to do so,
10  * subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be
13  * included in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23
24 #include <stdlib.h>
25 #include <lib/heap.h>
26 #include <err.h>
27 #include <debug.h>
28 #include <platform.h>
29 #include <platform/memmap.h>
30 #include <reg.h>
31 #include <string.h>
32
33 #include <platform/platform_p.h>
34
35 #define MC_SMMU_CONFIG_0                        0x10
36 #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE    0
37 #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE     1
38
39 #define MC_SMMU_TLB_CONFIG_0                    0x14
40 #define MC_SMMU_TLB_CONFIG_0_RESET_VAL          0x20000010
41
42 #define MC_SMMU_PTC_CONFIG_0                    0x18
43 #define MC_SMMU_PTC_CONFIG_0_RESET_VAL          0x2000003f
44
45 #define MC_SMMU_TLB_FLUSH_0                     0x30
46 #define TLB_FLUSH_VA_MATCH_ALL          0
47 #define TLB_FLUSH_ASID_MATCH_DISABLE    0
48 #define TLB_FLUSH_ASID_MATCH_SHIFT      31
49 #define MC_SMMU_TLB_FLUSH_ALL                   \
50         (TLB_FLUSH_VA_MATCH_ALL |               \
51         (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
52
53 #define MC_SMMU_PTC_FLUSH_0                     0x34
54 #define MC_SMMU_PTC_FLUSH_ALL                   0
55
56 #define MC_SMMU_ASID_SECURITY_0                 0x38
57
58 #define MC_SECURITY_CFG0_0                      0x70
59 #define MC_SECURITY_CFG1_0                      0x74
60
61 #define MC_SMMU_TRANSLATION_ENABLE_0_0          0x228
62 #define MC_SMMU_TRANSLATION_ENABLE_1_0          0x22c
63 #define MC_SMMU_TRANSLATION_ENABLE_2_0          0x230
64
65 #define TRANSLATION_ENABLE      (~0)
66 #define ASID_SECURITY           (0)
67
68 static uint32_t platform_sec_base;
69 static uint32_t platform_sec_size;
70
71 static void init_smmu_hw()
72 {
73         uintptr_t mc_base = TEGRA_MC_BASE;
74
75         /* allow translations for all MC engines */
76         *REG32(mc_base + MC_SMMU_TRANSLATION_ENABLE_0_0) = TRANSLATION_ENABLE;
77         *REG32(mc_base + MC_SMMU_TRANSLATION_ENABLE_1_0) = TRANSLATION_ENABLE;
78         *REG32(mc_base + MC_SMMU_TRANSLATION_ENABLE_2_0) = TRANSLATION_ENABLE;
79
80         *REG32(mc_base + MC_SMMU_ASID_SECURITY_0) = ASID_SECURITY;
81
82         *REG32(mc_base + MC_SMMU_TLB_CONFIG_0) = MC_SMMU_TLB_CONFIG_0_RESET_VAL;
83         *REG32(mc_base + MC_SMMU_PTC_CONFIG_0) = MC_SMMU_PTC_CONFIG_0_RESET_VAL;
84
85         /* flush PTC and TLB */
86         *REG32(mc_base + MC_SMMU_PTC_FLUSH_0) = MC_SMMU_PTC_FLUSH_ALL;
87         (void) *REG32(mc_base + MC_SMMU_CONFIG_0);      /* read to flush writes */
88         *REG32(mc_base + MC_SMMU_TLB_FLUSH_0) = MC_SMMU_TLB_FLUSH_ALL;
89
90         /* enable SMMU */
91         *REG32(mc_base + MC_SMMU_CONFIG_0) = MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE;
92         (void) *REG32(mc_base + MC_SMMU_CONFIG_0);      /* read to flush writes */
93 }
94
95 void platform_secure_dram_aperture()
96 {
97         *REG32(TEGRA_MC_BASE + MC_SECURITY_CFG0_0) = platform_sec_base;
98         *REG32(TEGRA_MC_BASE + MC_SECURITY_CFG1_0) = (platform_sec_size >> 20);
99 }
100
101 void platform_init_memory(uint32_t sec_base, uint32_t sec_size)
102 {
103         platform_sec_base = sec_base;
104         platform_sec_size = sec_size;
105
106         init_smmu_hw();
107 }
108
109 void platform_restore_memory()
110 {
111         init_smmu_hw();
112         platform_secure_dram_aperture();
113 }